1. Field of the Invention
The present invention relates to a synchronizing circuit, and more particularly, to a synchronizing circuit in which a clock signal supplied from an external device is divided into a plurality of internal clock signals having different periods, so that the internal clock signals can be synchronously output.
2. Description of the Related Art
In a recent image processing technology, e.g., a MUSE (multiple sub-Nyquist sample encoding) decoder in a HDTV (high definition television), etc., it is necessary to incorporate a synchronizing circuit which is adapted to divide the frequency of a clock signal supplied from an external device into a plurality of internal clock signals having different periods and output the same.
In a conventional circuit (apparatus) in which plurality of clock signals (internal clock signals) whose frequencies (periods) are different from each other are necessary, if the internal clock signals have frequencies that are even times one another, the internal clock signals can be easily synchronized, but if the frequencies are in a relation of odd-number multiple of one another, it is difficult to synchronize the internal clock signals. To solve this, it is known in a synchronizing circuit to use a reset signal in order to synchronize the internal clock signals, regardless of the relationship of the frequency therebetween.
Namely, the conventional synchronizing circuit is, for example, constructed such that the internal clock signals are synchronized upon resetting using a reset signal. However, to synchronize the internal clock signals using the reset signal, a reset terminal must be provided as an external input signal terminal of the circuit or system. Further, it is also necessary to provide wiring for supplying the reset signals. The wiring for the reset signals includes not only a wiring within the semiconductor integrated circuit (IC), but also a wiring provided on a circuit board for the IC.
Therefore, it is necessary to additionally provide a reset terminal and wiring for the reset signals in a known synchronizing circuit. Further, in the conventional synchronizing circuit, reset signal generating circuit is necessary for generating the reset signal. The problems of the related art will be explained hereinafter in detail with reference to the accompanying drawings.